1. Field of the Invention
This invention relates generally to semiconductor manufacturing, and, more particularly, to a method, system, and apparatus for performing process control on a downstream process based upon analysis of an upstream process.
2. Description of the Related Art
The technology explosion in the manufacturing industry has resulted in many new and innovative manufacturing processes. Today's manufacturing processes, particularly semiconductor manufacturing processes, call for a large number of important steps. These process steps are usually vital, and therefore, require a number of inputs that are generally fine-tuned to maintain proper manufacturing control.
The manufacture of semiconductor devices requires a number of discrete process steps to create a packaged semiconductor device from raw semiconductor material. The various processes, from the initial growth of the semiconductor material, the slicing of the semiconductor crystal into individual wafers, the fabrication stages (etching, doping, ion implanting, or the like), to the packaging and final testing of the completed device, are so different from one another and specialized that the processes may be performed in different manufacturing locations that contain different control schemes.
Generally, a set of processing steps is performed across a group of semiconductor wafers, sometimes referred to as a lot. For example, a process layer that may be composed of a variety of different materials may be formed across a semiconductor wafer. Thereafter, a patterned layer of photoresist may be formed across the process layer using known photolithography techniques. Typically, an etch process is then performed across the process layer using the patterned layer of photoresist as a mask. This etching process results in the formation of various features or objects in the process layer. Such features may be used as, for example, a gate electrode structure for transistors. Many times, trench isolation structures are also formed in various regions of the semiconductor wafer to create electrically isolated areas across a semiconductor wafer. One example of an isolation structure that can be used is a shallow trench isolation (STI) structure.
The manufacturing tools within a semiconductor manufacturing facility typically communicate with a manufacturing framework or a network of processing modules. Each manufacturing tool is generally connected to an equipment interface. The equipment interface is connected to a machine interface to which a manufacturing network is connected, thereby facilitating communications between the manufacturing tool and the manufacturing framework. The machine interface can generally be part of an advanced process control (APC) system. The APC system initiates a control script, which can be a software program that automatically retrieves the data needed to execute a manufacturing process.
FIG. 1 illustrates a typical semiconductor wafer 105. The semiconductor wafer 105 typically includes a plurality of individual semiconductor die 103 arranged in a grid 150. Using known photolithography processes and equipment, a patterned layer of photoresist may be formed across one or more process layers that are to be patterned. As part of the photolithography process, an exposure process is typically performed by a stepper on approximately one to four die 103 locations at a time, depending on the specific photomask employed. The patterned photoresist layer can be used as a mask during etching processes, wet or dry, performed on the underlying layer or layers of material, e.g., a layer of polysilicon, metal, or insulating material, to transfer the desired pattern to the underlying layer. The patterned layer of photoresist is comprised of a plurality of features, e.g., line-type features or opening-type features that are to be replicated in an underlying process layer. Additionally, an ion implant process may be performed on the semiconductor wafer 105 to form various doped regions in the semiconducting substrate of the semiconductor wafer 105.
When processing semiconductor wafers 105, various process steps are sequentially performed on the semiconductor wafers 105. Errors resulting from one process may be mitigated by adjusting a subsequent process accordingly. This is known as feed-forward control. Turning now to FIG. 2, a flowchart depiction of a state-of-the-art method for performing feed-forward control is illustrated. One or more semiconductor wafers 105 in a wafer lot are processed by a processing system (block 210). Upon processing the semiconductor wafers 105, the processing system acquires metrology data from one or more selected wafers from the wafer lot (block 220). The metrology data may include quantitative measurements of various factors, such as film thickness, trench depth, and the like. Upon acquisition of metrology data, a quantitative analysis is performed on the metrology data (block 230). Often, the quantitative analysis includes a comparison of the quantitative results of the metrology data to predetermined, expected data. Based upon the quantitative analysis, a determination is made whether the measurements relating to the metrology data fall within a quantitative range of acceptable values (block 240). When the process system determines that the measurements do not fall within the predetermined allowable quantitative range, a feed-forward adjustment (block 250) to a subsequent downstream process may be performed to compensate for, or to mitigate, the error discovered on the wafer as a result of the previous process. If it is determined that the measurements do fall within the predetermined allowable quantitative range, then the feed-forward adjustment is not performed and the downstream process may then be performed on the semiconductor wafers 105 (block 260).
Among the problems associated with state-of-the-art methodology includes the fact that the quantitative analysis may not provide for proper feed-forward adjustment to the downstream process. Simply quantitatively examining the values of various measurements may lead to feed-forward adjustments that may cause additional problems or fail to adequately compensate for the previous errors discovered. There may be a variety of factors why a particular metrology parameter may be outside a predetermined desirable range. However, merely evaluating the fact that particular metrology parameters are out of range and performing an adjustment to compensate for that fact may not adequately or efficiently compensate for such an error, or may even cause additional errors. Such errors may lead to a reduction in device performance levels and/or a reduction in production yields.
The present invention is directed to overcoming, or at least reducing, the effects of, one or more of the problems set forth above.